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- Digital IC Thermal Analysis
The FireBolt thermal simulator computes full-chip temperatures with resolution down to the device and interconnect levels, and integrates smoothly into standard digital IC design flows. The software is fast and scalable, with the capacity to handle very large designs.
The output is a full-chip, 3-D temperature map, which can be used to reveal hotspots and excessive temperature variations. The temperature data also can be used to add thermal awareness to power, timing and electromigration analysis tools.
To run FireBolt, you need to provide a thermal technology file (die stack-up) for the foundry process, and thermal information for the package. FireBolt obtains the design layout and the power source information from your design environment to create a full 3-D temperature analysis of the design. It outputs instance-specific temperatures, wire temperatures and device powers. This information can be annotated into simulation to determine the thermal impact on the circuit's performance and reliability.
FireBolt is intended for use at several points in the design flow, from floorplanning to final sign-off. In the early front-end stage it makes use of information at the block-level, such as the area estimates and power estimates. In the later, back-end stages, FireBolt has the capacity to complete the full analysis, even with many more metal shapes and large number of instances and their power dissipations.
Gradient is unique in its ability to calculate interconnect temperatures due to Joule heating, which allows designers to evaluate the impact on reliability due to electromigration failure.
FireBolt takes into account the influence of the package thermal characteristics on the die temperatures.
FireBolt runs in multiple modes that allow the user to trade off between speed and accuracy, and enables control on the levels of resolution.
FireBolt can be run in interactive GUI mode, allowing the user to navigate in three dimensions throughout the entire chip and to visually inspect the temperatures on the substrate and the metal layers. It can be also run in a text mode, allowing for scripting and integration of results into other analysis tools.
FireBolt is interoperable with existing analysis and implementation flows. It produces deterministic results for a given power distribution, which accounts for the electro-thermal effects within the chip, and fast enough to handle large, complex chip designs.
Visit our booth at the IEEE International 3D Systems Integration
Conference at the Hyatt Embarcadero, San Francisco, California.
Date: September 28-30, 2009
Please send email to: sales@gradient-da.com to schedule a demo session.
"Gradient's FireBolt with an integrated package thermal model is helping AMD to explore chip floorplan, fab process, and design scaling options in a unified manner. We're able to achieve thermal modeling resolution down to a single via which significantly enhances our electromigration avoidance capability."
Jim Brewer,
Global Analysis Manager,
Advanced Micro Devices
