RISKS

Uniform Temperature Assumptions Mismatched Length Scales Time Varying Temperature 3D IC
“Gradient is helping AMD achieve closure on interconnect electromigration verification and device reliability taking into account actual hot spot temperature and reduce unnecessary conservatism in designs. We’re able to achieve thermal modeling resolution down to a single via which significantly enhances our electromigration avoidance capability.”

Yuri Apanovich
Electrical Analysis Manager Advanced Micro Devices

Mismatched Length Scales

One Size Does Not Fit All

Engineers who take the “one size fits all” approach to thermal simulation may run the risk of missing hazards that are due to fine-grain temperature variations.

Different Applications, Different Scales

Microelectronics thermal performance is typically modeled at the millimeter scale of package and PCB features, which can amply predict the average chip temperature. Many chip designers assume that they are getting adequate thermal management using simulators that were built for package / PCB.

However, the submicron power sources and heat conduction paths within the modern chip can produce fine-grain temperature variations (ΔT), which can lead to IC reliability and performance issues. These issues may not be visible even using IR imaging or thermal simulation with 10µm resolution.

It is simply not practical for a single simulator to span the wide range of length scales -- from the millimeter scale of package and PCB, to the submicron scale of IC layout features. To bridge the two different physical length scales, you can use a package simulator to model the region outside the die (package and PCB) and produce the boundary conditions as seen at the die faces, and use an IC simulator to model the region inside the die.

Automation, Capacity, Resolution

  Ansys Icepak Mentor FloTHERM Apache Sentinel-TI Cadence Encounter Power System Synopsys Sentaurus Gradient
HeatWave
Package-Thermal
Simulation		 Coarse Coarse Coarse      
IC Full-Chip
Capacity		     Yes Yes   Yes
Device-Level
Resolution		 Fine       Fine Fine
Device-Level CAD Data Exchange Manual       Manual Layout, Power, Temperature


Risk Assesment

  • Does your chip have high performance transistors with high power densities and submicron features?
  • Can your thermal simulator resolve temperature spikes at your transistor feature sizes?
  • Can you model all the detailed layouts of your full chip, with distinct thermal properties for all the materials?
Request a Free ΔT Assessment