HeatWave™ computes the temperature inside the chip or 3D-IC by first building a solid-body heat conduction model of the domain. This thermal model is constructed with adaptive resolution, commensurate with the feature sizes of the power sources and heat conduction paths inside the chip.
Using Layout Data
The thermal model uses IC layout data (all the shapes on all the layers, as generated by layout tools such as Cadence Virtuoso), plus a thermal techfile containing the layer thicknesses and material properties, including their temperature dependencies. The model uses full-chip layout, because even non-functional geometries such as metal fill may significantly affect heat transport.
Using Power Data
Power sources are modeled as volumes dissipating specified power values (as generated by your circuit simulator). In the case of steady-state temperature simulation, this is the average power dissipated per circuit instance, which may be a transistor, a transistor segment, a standard cell or a macro instance.
Using Package Thermal Data
HeatWave calculates the temperature within the die (or die stack), containing structures with submicron feature sizes, so the thermal model requires similar resolution. A package macro model is used for the region outside the die (package and board) containing features at millimeter length scales. The package model bridges the two different physical length scales.
HeatWave takes into account the influence of the bond wires/bumps and the package thermal characteristics, including die-attach and ambient temperature. You may specify them as a set of 6 boundary thermal resistances or heat fluxes as seen at the die faces, as shown below.
HeatWave then computes the temperature using all of the above data, by numerically solving the heat diffusion equation within the chip or 3D-IC. Finally, it reports the volume-averaged temperature of all power sources, and design objects. Click here to see some results of temperature simulations.