Recent News Snippets

The paper "Using Thermal Analysis as a Tool to Aid Analog Floorplanning" won the People's Choice Award for "Track 9: Special Interest" at CDNLive! Silicon Valley 2007
- by David Schwan, RF Micro Devices (formerly Sirenza), 11 Sep. 2007

"We see more thermal variation at 45 nm ... each portion of the chip can operate at a different temperature rather than having a uniform temperature as is modeled today."
- Cadence's Vassilios Gerousis, interviewed on cdnusers.org, 10 Sep. 2007

"Today, power dissipation is the dominant performance-limiting factor in nanometer designs."
- EETimes Asia, 16 Jan. 2007

"Digital ICs can experience as much as a 50°C temperature variation across a die. And yet, even a 4°C gradient can cause a malfunction."
- Gradient's Rajit Chandra, quoted in EETimes, 19 June 2006

"Previous temperature-analysis methods have assumed a constant temperature throughout the chip, or, at worst, a minimal amount of distributed temperature."
- discussion of shortcomings that Gradient's CircuitFire product overcomes, Electronic Design, 11 May 2006

"Incompletely accounting for the physics of thermal effects in the design methodology results in unnecessary design costs due to failed parts."
- Chip Design, 3 April 2006

"Gradient Design Automation's FireBolt IC thermal analysis is unique in that it addresses thermal analysis from an IC-design perspective rather than a packaging or systems perspective."
- coverage of FireBolt winning the 2005 EDN Innovation award, EDN, 3 April 2006