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Nanoscale Thermal Simulation
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Avoid Hazards, and Improve Designs Significant temperature variations in a chip are caused by high power densities. Today’s digital and analog ICs can have very high power densities. Many ICs now in production are known to sustain temperature differences exceeding 30ºC within the die, with some exceeding 100ºC. Intra-die temperature variations are known to be hazardous. Moderate temperature differences of a few degrees Celsius can adversely affect transistor matching in voltage references, bias current sources, amplifiers, etc., and precision resistor-matching in data-converters. Temperature differences in the tens of degrees Celsius may lead to inefficiencies such as unbalanced drive in the different fingers of a power-transistor, or failures within the die such as electromigration in metal traces and vias near the hot devices.
Nanoscale Temperature Surface Plot. Thermally induced circuit failures and performance degradations that are not detected during the design phase may only be corrected after silicon re-spins. These are very costly remedies. Therefore, unless the detailed and accurate temperature data are known, designers must allow for thermal unknowns by increasing design margins, which is also very costly. It is far better for designers to know the detailed temperature profile within the chip during the design process. The information can provide early warnings for thermal hazards, such as hotspots and excessive temperature variations; it can also be used to improve design parameters. To ensure design quality, early warning of potential problems is essential to an effective design flow. The 3-D temperature profile within the die can be computed by thermal simulation of the physical design. Thermal simulation at the requisite high-resolution is practicable using the commercially available tools from Gradient now, and the physical-analysis results can help predict destructive failures, functional failures or parameter degradations. Gradient Design Automation Gradient is a software start-up that has pioneered accurate, fine-grain IC thermal analysis for chips, and stacked-die SiP. Basically, the risk factors for thermal challenges are ICs with high performance, high currents, and/or high voltages. So, our customer is a designer of chips with such risk factors. We provide a tool for him to screen the design for thermal issues, early enough for him to correct the problems. Because the detailed layout features inside a chip are very small, at the nanometer scale, we have to use modeling and solution techniques that are commensurate with such length-scales. Our simulator is built to fit into the standard EDA ecosystem and to make use of the existing design data, so that the user can maximize the automation and minimize extra work in using the new simulator. The results are 3-d temperature profiles with very high resolution and accuracy. The simulated 3-d temperature profiles provide unprecedented visibility for the designer, and help to reveal any thermally-induced circuit failures and performance degradations before tapeout, so that corrective actions can be taken. This helps the designer avoid thermal hazards, such as hotspots and excessive temperature variations. Our simulator doesn’t just take the design data, but it also contributes by adding temperature-awareness back to the design ecosystem, and this helps to improve electrical simulation accuracy and reals more opportunities to neutralize any adverse thermal effects on critical aspects of IC designs, such as analog circuitry mismatch, electromigration, leakage current, switching speed, and relative timing paths. So it also improves the chip design process. Gradient’s unique IC thermal analysis technology has been used to cover a wide range of applications: Digital SoC and Analog/Power/RF in steady-state and transient modes. It has been used for a wide range of functions: thermal analysis and sign-off; thermal validation at different design stages (floorplanning, P&R, package integration, etc.).
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Visit our booth at the IEEE International 3D Systems Integration
Conference at the Hyatt Embarcadero, San Francisco, California. Date: September 28-30, 2009 Please send email to: sales@gradient-da.com to schedule a demo session.
"We have deployed CircuitFire to IC designers in the High Performance Analog Division at TI. We have designers using it to predict peak temperature, temperature variation and the effects of temperature on electrical performance of critically matched devices. Thermal simulation has been used on process technologies ranging from standard CMOS to trench isolated SOI and BiCMOS processes."
Tom Vrotsos,
"Gradient's FireBolt with an integrated package thermal model is helping AMD to explore chip floorplan, fab process, and design scaling options in a unified manner. We're able to achieve thermal modeling resolution down to a single via which significantly enhances our electromigration avoidance capability."
Jim Brewer,
"We collaborated with Gradient on HeatWave, which is a full-chip transient electro-thermal simulator. Simulation results for a chip containing power transistors and temperature sensors, taken over a two second interval, correlated well with measured data."
Yves Depret, "Managing heat is important in high-power design. The thermal map of a circuit can be used as a floorplanning tool to reduce temperature deltas in sensitive areas of the design; this may translate to greater efficiency.
David Schwan, |
